1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device having a test mode driven by an external power supply potential.
2. Description of the Background Art
Conventionally, in a dynamic random access memory (hereinbelow, abbreviated as DRAM), packing density is being increased and power supply voltage is being decreased. For this purpose, the DRAM is provided with an internal power supply potential generating circuit for generating an internal power supply potential by dropping the external power supply potential. In the DRAM, to reject an early defective piece in which a defect occurs relatively early after shipment, a burn-in test is carried out before shipment. In the burn-in test, an internal power supply potential higher than that in a normal mode is applied, and data is written/read to/from each of memory cells under high-temperature environment. It accelerates the occurrence of a defective, so that an early defective piece can be prevented from being shipped.
FIG. 10 is a block diagram showing the configuration of such an internal power supply potential generating circuit 80 of a DRAM. In FIG. 10, the internal power supply potential generating circuit 80 includes a VPP generating circuit 81, a VDDS generating circuit 82, and a VDDP generating circuit 83.
The VPP generating circuit 81 includes, as shown in FIG. 11, a ring oscillator 84, a charge pump circuit 85, and a detector 86. The detector 86 receives both a potential VPP of a power supply node N85 and an internal power supply potential VDDS from the VDDS generating circuit 82. When VPP less than VDDS+2Vthn (where Vthn denotes a threshold voltage of an N-channel MOS transistor), the detector 86 sets a signal xcfx86E to the xe2x80x9cHxe2x80x9d level. When VPPxe2x89xa7VDDS+2Vthn, the detector 86 sets the signal xcfx86E to the xe2x80x9cLxe2x80x9d level. When the signal xcfx86E is at the xe2x80x9cHxe2x80x9d level, the ring oscillator 84 generates a clock signal CLK and supplies it to the charge pump circuit 85. When the signal xcfx86E is at the xe2x80x9cLxe2x80x9d level, the ring oscillator 84 is made inactive. The charge pump circuit 85 supplies a predetermined amount of positive charges to the power supply node N85 in response to the rising edge of the clock signal CLK.
When VPP less than VDDS+2Vthn, the positive charges are supplied from the charge pump circuit 85 to the power supply node N85. When VPPxe2x89xa7VDDS+2Vthn, the supply of power from the charge pump circuit 85 to the power supply node N85 is stopped. The potential VPP at the power supply node N85 is therefore maintained at VDDS+2Vthn. The internal power supply potential VPP is used as a wordline selection level.
The VDDS generating circuit 82 includes, as shown in FIG. 12, an operational amplifier 90, a constant current source 91, a variable resistive element 92, and P-channel MOS transistors 93 and 94. The constant current source 91 and the variable resistive element 92 are connected in series between a line of the external power supply potential VCC and a line of a ground potential VSS. The P-channel MOS transistor 93 has the source for receiving an external reference potential VRSxe2x80x2, the drain connected to a node N91 between the constant current source 91 and the variable resistive element 92, and the gate for receiving a test signal ITE.
The P-channel MOS transistor 94 is connected between the line of the external power supply potential VCC and a power supply node N94. The operational amplifier 90 has an inversion input terminal connected to the node N91, a non-inversion input terminal connected to the power supply node N94, and the output terminal connected to the gate of the P-channel MOS transistor 94. The operational amplifier 90 and the P-channel MOS transistor 94 construct a voltage follower for maintaining the potential VDDS at the power supply node N94 at the same level as the potential at the node N91. The internal power supply potential VDDS is applied to a sense amplifier.
At the time of tuning, the test signal /TE is set to the xe2x80x9cHxe2x80x9d level as an inactivate level, and the P-channel MOS transistor 93 is made non-conductive. The resistance value of the variable resistive element 92 is tuned so that the internal power supply potential VDDS becomes equal to a predetermined value VRS.
At the time of a burn-in test, the test signal /TE is set to the xe2x80x9cHxe2x80x9d level as an activate level, the P-channel MOS transistor 93 is made conductive, and the internal power supply potential VDDS becomes equal to the external reference potential VRSxe2x80x2 ( greater than VRS). The internal power supply potential VPPS becomes equal to VRSxe2x80x2+2Vthn. In normal operation, the test signal /TE is set to the xe2x80x9cHxe2x80x9d level as an inactivate level, the P-channel MOS transistor 93 is made non-conductive, and the internal power supply potential VDDS becomes VRS. The internal power supply potential VPP becomes equal to VRS+2Vthn.
The VDDP generating circuit 83 includes, as shown in FIG. 13, an operational amplifier 95, a constant current source 96, a variable resistive element 97, P-channel MOS transistors 98 and 99, an N-channel MOS transistor 100, and an inverter 101. The constant current source 96 and the variable resistive element 97 are connected in series between the line of the external power supply potential VCC and the line of the ground potential VSS. The P-channel MOS transistor 99 is connected between the line of the external power supply potential VCC and a power supply node N98. The operational amplifier 95 has an inversion input terminal connected to a node N96 between the constant current source 96 and the variable resistive element 97, a non-inversion input terminal connected to the power supply node N98, and an output terminal connected to the gate of the P-channel MOS transistor 99. The operational amplifier 95 and the P-channel MOS transistor 99 construct a voltage follower which maintains the potential VDDP of the power supply node N98 to the level same as the potential of the node N96. The internal power supply potential VDDP is supplied to peripheral circuits.
The P-channel MOS transistor 98 is connected in parallel with the constant current source 96. The N-channel MOS transistor 100 is connected between the gate of the P-channel MOS transistor 99 and the line of the ground potential VSS. The test signal ITE is directly supplied to the gate of the P-channel MOS transistor 98 and also to the gate of the N-channel MOS transistor 100 via the inverter 101.
At the time of tuning, the test signal /TE is set to the xe2x80x9cHxe2x80x9d level as an inactivate level, and the MOS transistors 98 and 100 are made non-conductive. The resistance value of the variable resistive element 97 is tuned so that the internal power supply potential VDDP becomes equal to a predetermined value VRP ( greater than VRS).
At the time of a burn-in test, the test signal /TE is set to the xe2x80x9cLxe2x80x9d level as an activate level, the MOS transistors 98 and 100 are made conductive, and the internal power supply potential VDDP becomes equal to the external power supply potential VCC. In normal operation, the test signal /TE is set to the xe2x80x9cHxe2x80x9d level as an inactivate level, the MOS transistors 98 and 100 are made non-conductive, and the internal power supply potential VDDP becomes VRP.
In short, in normal operation, VPP=VRS+2Vthn, VDDS=VRS, and VDDP=VRP. At the time of the burn-in test, VPP=VRSxe2x80x2+2Vthn, VDDS=VRSxe2x80x2, and VDDP=VCC. VRS and VRP are tuned.
In the conventional internal power supply potential generating circuit 80, however, VPP is equal to VDDS+2Vthn. Consequently, VPP and VDDS cannot be set independently of each other. Occurrence of an early defective in a circuit portion to which VPP is applied and that in a circuit portion to which VDDS is applied cannot be separately accelerated, so that test efficiency is low.
The resistance values of the two variable resistive elements 92 and 97 have to be tuned. The tuning is, however, troublesome.
It is, therefore, an object of the invention to provide a semiconductor device having high test efficiency.
Another object of the invention is to provide a semiconductor device capable of easily adjusting an internal reference potential.
A semiconductor device according to the invention includes: a first reference potential generating circuit of which output potential is adjustable, for outputting a first internal reference potential which is lower than the external power supply potential; a first power supply circuit for maintaining a first power supply node at the first internal reference potential in a normal operation mode, and maintaining the first power supply node at an external reference potential in a test mode; a second power supply circuit for maintaining a second power supply node at a boosted potential higher than the first internal reference potential by a predetermined first voltage in the normal operation mode, and supplying the external power supply potential to the second power supply node in the test mode; a level shifting circuit for outputting a potential obtained by level-shifting the potential of the first power supply node by a predetermined second voltage to the external power supply potential side; a third power supply circuit for maintaining a third power supply node at an output potential of the level shifting circuit; and an internal circuit for receiving a drive power from the first to third power supply circuits via the first to third power supply nodes and performing a predetermined operation. Consequently, in the test mode, the first power supply node is maintained at the first external reference potential and the second power supply node is maintained at the external power supply potential, so that occurrence of a defect in the circuit portion to which the potential of the first power supply node is applied and that in the circuit portion to which the potential of the second power supply node is applied can be accelerated separately from each other. Thus, the test efficiency is increased. Since it is sufficient to adjust only the first internal reference potential, as compared with the conventional technique in which two internal reference potentials have to be adjusted, the internal reference potential can be easily adjusted.
Preferably, the first reference potential generating circuit includes: a first constant current source connected between a line of the external power supply potential and a first output node, for supplying a predetermined first current to the first output node; and a first variable resistive element of which resistance value is adjustable, which is connected between the first output node and a line of a ground potential. In this case, by adjusting the resistance value of the first variable resistive element, the first internal reference potential can be adjusted.
Preferably, the second power supply circuit includes: a charge pump circuit which is activated when a potential of the second power supply node is lower than the boosted potential in the normal operation mode and supplies a current to the first power supply node; and a switching element which is connected between a line of the external power supply potential and the second power supply node and is made conductive in the test mode. In this case, the second power supply circuit can be easily constructed.
Preferably, the level shifting circuit includes: a second constant current source which is connected between the line of the external power supply potential and a second output node and supplies a predetermined second current to the second output node; and a transistor connected between the second output node and the line of the ground potential, of which input electrode receives the potential of the first power supply node. In this case, the predetermined second voltage is used as a threshold voltage of the transistor.
Preferably, there is provided a second reference potential generating circuit of which output potential is adjustable, for outputting a second internal reference potential which lies between the external power supply potential and the first internal reference potential, and the third power supply circuit maintains the third power supply node at the second internal reference potential in the normal operation mode, and maintains the third power supply node at an output potential of the level shifting circuit in the test mode. In this case, the potential of the third power supply node in the normal operation mode can be finely adjusted, so that the internal circuit is allowed to operate with high precision.
Preferably, the semiconductor device further includes: a second reference potential generating circuit of which output potential is adjustable, for outputting a second internal reference potential which lies between the external power supply potential and the first internal reference potential; and a selecting circuit for selecting either an output potential of the level shifting circuit or the second internal reference potential, and the third power supply circuit maintains the third power supply node at a potential selected by the selecting circuit. In this case, when the output potential of the level shifting circuit is selected, the internal reference potential can be easily adjusted but the precision of the operation of the internal circuit deteriorates. On the other hand, when the second reference potential is selected, the adjustment of the internal reference potential becomes troublesome, but the internal circuit is allowed to operate with high precision.
Preferably, the second reference potential generating circuit includes: a third constant current source connected between a line of the external power supply potential and a third output node, for supplying a predetermined third current to the third output node; and a second variable resistive element connected between the third output node and the line of the ground potential, of which resistance value is adjustable. In this case, by adjusting the resistance value of the second variable resistive element, the second internal reference potential can be adjusted.
Preferably, the semiconductor device is a semiconductor memory device, and a sense amplifier receives a drive power from the first power supply circuit via the first power supply node, the wordline selected by the row selecting circuit receives a drive power from the second power supply circuit via the second power supply node, and the row selecting circuit, the column selecting circuit, and the write/read circuit receive a drive power from the third power supply circuit via the third power supply node. The present invention is particularly effective on this case.
A semiconductor device according to another aspect of the invention includes: a first power supply circuit for generating a first internal power supply potential lower than the external power supply potential; a level shifting circuit for outputting a potential obtained by level-shifting the first internal power supply potential by a predetermined voltage to the external power supply potential side; a second power supply circuit for maintaining a second internal power supply potential at the same level as a predetermined reference potential in a normal operation mode, and maintaining the second internal power supply potential at the same level as an output potential of the level shifting circuit in a test mode; and an internal circuit which is driven by first and second internal power supply potentials generated by the first and second power supply circuits and performs a predetermined operation. In the test mode, the second internal power supply potential is maintained at a potential obtained by level-shifting the first internal power supply potential only by a predetermined voltage, so that the level of the second,internal power supply potential can be easily set, and the test efficiency is increased. In the normal operation mode, since the second internal power supply potential is maintained at the predetermined reference potential, the internal circuit is allowed to operate with high precision.
Preferably, the predetermined reference potential is a potential between the external power supply potential and the first internal power supply potential. In this case, the reference potential can easily be generated.
Preferably, the semiconductor device according to the present invention further includes a reference potential generating circuit of which output potential is adjustable, for outputting the predetermined reference potential. The reference potential generating circuit includes: a first constant current source connected between a line of the external power supply potential and a first output node, for supplying a predetermined first current to the first output node; and a variable resistive element connected between the first output node and a line of a ground potential, of which resistance value is adjustable. In this case, by adjusting the resistance value of the variable resistive element, the potential can be adjusted to the reference potential.
Preferably, the level shifting circuit includes: a second constant current source connected between a line of the external power supply potential and a second output node, for supplying a predetermined second current to the second output node; and a first transistor connected between the second output node and the line of the ground potential, of which input electrode receives the first internal power supply potential. In this case, the predetermined voltage is a threshold voltage of the first transistor.
Preferably, the second power supply circuit includes: a switching circuit for supplying the reference potential to a third output node in the normal operation mode and supplying an output potential of the level shifting circuit to the third output node in the test mode; a second transistor connected between the line of the external power supply potential and a fourth output node; and a control circuit for controlling an input voltage of the second transistor so that the potentials of the third and fourth output nodes coincide with each other, and the potential of the fourth output node becomes equal to the second internal power supply potential. In this case, the second power supply circuit can be easily constructed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.